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15
FN1547.8
October 29, 2007
Read/Write Data (See Figure 10)
Read/Write data follows the Address/Control byte.
Watchdog Reset (See Figure 11)
When watchdog operation is selected, CE must be toggled
periodically or a CPU reset will be outputted.
Address and Data
Data transfers can occur one byte at a time (Figure 12) or in
a multibyte burst mode (Figure 13). After the Real-Time
Clock enabled, an Address/Control word is sent to set the
CLOCK or RAM and select the type of operation (i.e., Read
or Write). For a single-byte Read or Write, one byte is
transferred to or from the Clock Register or RAM location
specified in the Address/Control byte and the Real-Time
Clock is then disabled. Write cycle causes the latched Clock
Register or RAM address to automatically increment.
Incrementing continues after each transfer until the device is
disabled. After incrementing to 1FH the address will “wrap”
to 00H and continue. Therefore, when the RAM is selected
the address will “wrap” to 00H and when the clock is
selected the address will “wrap” 20H.
D7
D6
D5
D4
D3
D2
D1
D0
7
6
54
32
1
0
BIT
D2
D1
D0
D3
D4
D5
D6
D7
D2
D1
D0
D3
D4
D5
D6
D7
CE
SCK (NOTE)
MOSI
MISO
NOTE: SCK can be either polarity.
FIGURE 10. READ/WRITE DATA TRANSFER WAVEFORMS
CE
SERVICE
TIME
SERVICE
TIME
SCK
CPUR
FIGURE 11. WATCHDOG OPERATION WAVEFORMS
CDP68HC68T1
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